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1/20 not for new design november 2001 this is information on a product still in production but not recommended for new designs. m24256-a 256 kbit serial i2c bus eeprom with two chip enable lines this device is now designated as not for new de- sign. please use the m24256-b in all future de- signs (as described in application note an1470). n compatible with i 2 c extended addressing n two wire i 2 c serial interface supports 400 khz protocol n single supply voltage: C 4.5v to 5.5v for m24256-a C 2.5v to 5.5v for m24256-aw n 2 chip enable inputs: up to four memories can be connected to the same i 2 c bus n hardware write control n byte and page write (up to 64 bytes) n random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up behavior n more than 100,000 erase/write cycles n more than 40 year data retention description these i 2 c-compatible electrically erasable pro- grammable memory (eeprom) devices are orga- nized as 32kx8 bits, and operate down to 2.5 v (for the m24256-aw). the m24256-a is available in plastic dual-in-line, plastic small outline and thin shrink small out- figure 1. logic diagram ai02271c sda v cc m24256-a wc scl v ss 2 e0-e1 table 1. signal names e0, e1 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground pdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop14 (dl) 169 mil width 8 1 8 1 so8 (mw) 200 mil width 8 1 sbga sbga7 (ea) 140 x 90 mil
m24256-a 2/20 figure 2a. dip connections note: 1. nc = not connected figure 2b. so connections note: 1. nc = not connected sda v ss scl wc e1 e0 v cc nc ai02273c m24256-a 1 2 3 4 8 7 6 5 1 ai02272c 2 3 4 8 7 6 5 sda v ss scl wc e1 e0 v cc nc m24256-a figure 2c. tssop connections note: 1. nc = not connected figure 2d. sbga connections (top view) 1 ai02388c 2 3 4 14 9 10 8 sda v ss nc scl e0 wc m24256-a nc e1 nc nc nc nc nc 5 6 7 12 13 11 v cc ai03760 scl v ss sda wc v cc m24256-a s1 s0 table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. ipc/jedec j-std-020a 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) 4. eiaj ic-121 (condition c) (200 pf, 0 w ) symbol parameter value unit t a ambient operating temperature C40 to 125 c t stg storage temperature C65 to 150 c t lead lead temperature during soldering pdip: 10 seconds so: 20 seconds (max) 2 tssop: 20 seconds (max) 2 260 235 235 c v io input or output range C0.6 to 6.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 3 4000 v electrostatic discharge voltage (machine model) 4 200 v
3/20 m24256-a line packages. the m24256-a is also available in a chip-scale (sbga) package. these memory devices are compatible with the i 2 c extended memory standard. this is a two wire serial interface that uses a bi-directional data bus and serial clock. the memory carries a built-in 4- bit unique device type identifier code (1010) in accordance with the i 2 c bus definition. the memory behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and rw bit (as described in table 3), terminated by an acknowledge bit. when writing data to the memory, the memory in- serts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and af- ter a noack for read. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on re- set (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are dis- abled C the device will not respond to any com- mand. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. signal description serial clock (scl) the scl input pin is used to strobe all data in and out of the memory. in applications where this line is used by slaves to synchronize the bus to a slow- er clock, the master must have an open drain out- put, and a pull-up resistor must be connected from the scl line to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the master has a push-pull (rather than open drain) output. serial data (sda) the sda pin is bi-directional, and is used to trans- fer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from the sda bus to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). chip enable (e1, e0) these chip enable inputs are used to set the value that is to be looked for on the two least significant bits (b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss to establish the device select code. when unconnected, the e1 and e0 inputs are internally read as v il (see table 7 and table 8) write control (wc ) the hardware write control pin (wc ) is useful for protecting the entire contents of the memory from inadvertent erase/write. the write control signal is used to enable (wc =v il ) or disable (wc =v ih ) write instructions to the entire memory area. when figure 3. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz
m24256-a 4/20 unconnected, the wc input is internally read as v il , and write operations are allowed. when wc =1, device select and address bytes are acknowledged, data bytes are not acknowl- edged. please see the application note an404 for a more detailed description of the write control feature. device operation the memory device supports the i 2 c protocol. this is summarized in figure 4, and is compared with other serial bus protocols in application note an1001 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the master, and the other as the slave. a data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. the memory device is always a slave device in all communica- tion. start condition start is identified by a high to low transition of the sda line while the clock, scl, is stable in the high state. a start condition must precede any data transfer command. the memory device con- tinuously monitors (except during a programming cycle) the sda and scl lines for a start condi- tion, and will not respond unless one is given. stop condition stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition terminates communica- tion between the memory device and the bus mas- ter. a stop condition at the end of a read command, after (and only after) a noack, forces the memory device into its standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. figure 4. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
5/20 m24256-a acknowledge bit (ack) an acknowledge signal is used to indicate a suc- cessful byte transfer. the bus transmitter, whether it be master or slave, releases the sda bus after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls the sda bus low to acknowledge the receipt of the eight data bits. data input during data input, the memory device samples the sda bus signal on the rising edge of the clock, scl. for correct device operation, the sda signal must be stable during the clock low-to-high transi- tion, and the data must change only when the scl line is low. memory addressing to start communication between the bus master and the slave memory, the master must initiate a start condition. following this, the master sends the 8-bit byte, shown in table 3, on the sda bus line (most significant bit first). this consists of the 7-bit device select code, and the 1-bit read/write designator (rw ). the device select code is fur- ther subdivided into: a 4-bit device type identifier, and a 3-bit chip enable address (0, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to four memory devices can be connected on a single i 2 c bus. each one is given a unique 2-bit code on its chip enable inputs. when the device select code is received on the sda bus, the mem- ory only responds if the chip select code is the same as the pattern applied to its chip enable pins. the 8 th bit is the rw bit. this is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding mem- ory gives an acknowledgment on the sda bus dur- ing the 9 th bit time. if the memory does not match the device select code, it deselects itself from the bus, and goes into stand-by mode. there are two modes both for read and write. these are summarized in table 6 and described later. a communication between the master and the slave is ended with a stop condition. each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte (ta- ble 4) is sent first, followed by the least significant byte (table 5). bits b15 to b0 form the address of the byte in memory. bit b15 is treated as dont care bits on the m24256-a memory. write operations following a start condition the master sends a device select code with the rw bit set to 0, as shown in table 6. the memory acknowledges this, and waits for two address bytes. the memory re- table 3. device select code 1 note: 1. the most significant bit, b7, is sent first. device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1 0 1 0 0 e1 e0 rw table 4. most significant byte note: 1. b15 is treated as dont care on the m24256-a series. table 5. least significant byte b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 6. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 data bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 64 start, device select, rw = 0
m24256-a 6/20 figure 5. write mode sequences with wc =1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120c page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack sponds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if the wc input pin is taken high. any write command with wc =1 (during a period of time from the start condition until the end of the two address bytes) will not modify the memory contents, and the ac- companying data bytes will not be acknowledged, as shown in figure 5. byte write in the byte write mode, after the device select code and the address bytes, the master sends one data byte. if the addressed location is write protected by the wc pin, the memory replies with a noack, and the location is not modified. if, in- stead, the wc pin has been held at 0, as shown in figure 6, the memory replies with an ack. the master terminates the transfer by generating a stop condition. page write the page write mode allows up to 64 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the most significant memory address bits (b14-b6 for the m24256-a) are the same. if more bytes are sent than will fit up to the end of the row, a condition known as roll-over occurs. data starts to become overwritten (in a way not formally spec- ified in this data sheet). the master sends from one up to 64 bytes of data, each of which is acknowledged by the memory if the wc pin is low. if the wc pin is high, the con- tents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 6 least significant bits only) is incremented. the transfer is terminated by the master generating a stop condition. when the master generates a stop condition im- mediately after the ack bit (in the 10 th bit time
7/20 m24256-a figure 6. write mode sequences with wc =0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106b page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time does not trig- ger the internal write cycle. during the internal write cycle, the sda input is disabled internally, and the device does not re- spond to any requests. minimizing system delays by polling on ack during the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells. the maxi- mum write time (t w ) is shown in table 9, but the typical time is shorter. to make use of this, an ack polling sequence can be used by the master. the sequence, as shown in figure 7, is: C initial condition: a write is in progress. C step 1: the master issues a start condition followed by a device select code (the first byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the mas- ter goes back to step 1. if the memory has ter- minated the internal write cycle, it responds with an ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during step 1). read operations read operations are performed independently of the state of the wc pin. random address read a dummy write is performed to load the address into the address counter, as shown in figure 8. then, without sending a stop condition, the mas- ter sends another start condition, and repeats the device select code, with the rw bit set to 1. the memory acknowledges this, and outputs the contents of the addressed byte. the master must not acknowledge the byte output, and terminates the transfer with a stop condition.
m24256-a 8/20 the output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter rolls-over and the memory continues to output data from memory address 00h. acknowledge in read mode in all read modes, the memory waits, after each byte read, for an acknowledgment during the 9 th bit time. if the master does not pull the sda line low during this time, the memory terminates the data transfer and switches to its stand-by state. current address read the device has an internal address counter which is incremented each time a byte is read. for the current address read mode, following a start condition, the master sends a device select code with the rw bit set to 1. the memory acknowl- edges this, and outputs the byte addressed by the internal address counter. the counter is then in- cremented. the master terminates the transfer with a stop condition, as shown in figure 8, with- out acknowledging the byte output. sequential read this mode can be initiated with either a current address read or a random address read. the master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. to terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a stop condition. figure 7. write cycle polling flowchart using ack write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
9/20 m24256-a figure 8. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 4 th bytes) must be identical. start dev sel * byte addr byte addr start dev sel data out 1 ai01105c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24256-a 10/20 table 7. dc characteristics (t a = C40 to 85 c; v cc = 4.5 to 5.5 v or 2.5 to 5.5 v) table 8. input parameters 1 (t a = 25 c, f = 400 khz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma -w series: v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v 10 a -w series: v in = v ss or v cc , v cc = 2.5 v 2 a v il input low voltage (scl, sda) C0.3 0.3v cc v v ih input high voltage (scl, sda) 0.7v cc v cc +1 v v il input low voltage (e0, e1, wc ) C0.3 0.5 v v ih input high voltage (e0, e1, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v -w series: i ol = 2.1 ma, v cc = 2.5 v 0.4 v symbol parameter test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l input impedance (e1, e0, wc ) v in 0.5 v 50 k w z h input impedance (e1, e0, wc )v in 3 0.7v cc 500 k w t ns pulse width ignored (input filter on scl and sda) single glitch 100 ns
11/20 m24256-a table 9. ac characteristics note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. symbol alt. parameter m24256-a unit v cc =4.5 to 5.5 v t a =C40 to 85c v cc =2.5 to 5.5 v t a =C40 to 85c minmaxminmax t ch1ch2 t r clock rise time 300 300 ns t cl1cl2 t f clock fall time 300 300 ns t dh1dh2 2 t r sda rise time 20 300 20 300 ns t dl1dl2 2 t f sda fall time 20 300 20 300 ns t chdx 1 t su:sta clock high to input transition 600 600 ns t chcl t high clock pulse width high 600 600 ns t dlcl t hd:sta input low to clock low (start) 600 600 ns t cldx t hd:dat clock low to input transition 0 0 s t clch t low clock pulse width low 1.3 1.3 s t dxcx t su:dat input transition to clock transition 100 100 ns t chdh t su:sto clock high to input high (stop) 600 600 ns t dhdl t buf input high to input low (bus free) 1.3 1.3 s t clqv 3 t aa clock low to data out valid 200 900 200 900 ns t clqx t dh data out hold time after clock low 200 200 ns f c f scl clock frequency 400 400 khz t w t wr write time 10 10 ms table 10. ac measurement conditions input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc figure 9. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
m24256-a 12/20 figure 10. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
13/20 m24256-a table 11. ordering information scheme note: 1. sbga7 p ackage available only for the m24256-a w ea 6 t example: m24256 C a w mn 6 t memory capacity option 256 256 kbit (32k x 8) t tape and reel packing temperature range 6 C40 c to 85 c operating voltage package blank 4.5 v to 5.5 v bn pdip8 (0.25 mm frame) w 2.5 v to 5.5 v mn so8 (150 mil width) mw so8 (200 mil width) dl tssop14 (169 mil width) ea sbga7 1 ordering information devices are shipped from the factory with the memory content set at all 1s (ffh). the notation used for the device number is as shown in table 11. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office.
m24256-a 14/20 pdip8 C 8 pin plastic dip, 0.25mm lead frame note: 1. drawing is not to scale. pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e pdip8 C 8 pin plastic dip, 0.25mm lead frame symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
15/20 m24256-a so8 narrow C 8 lead plastic small outline, 150 mils body width note: drawing is not to scale. so-a e n cp b e a d c l a1 a 1 h h x 45? so8 narrow C 8 lead plastic small outline, 150 mils body width symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
m24256-a 16/20 so8 wide C 8 lead plastic small outline, 200 mils body width note: drawing is not to scale. so-b e n cp b e a2 d c l a1 a h a 1 so8 wide C 8 lead plastic small outline, 200 mils body width symb. mm inches typ. min. max. typ. min. max. a 2.03 0.080 a1 0.10 0.25 0.004 0.010 a2 1.78 0.070 b 0.35 0.45 0.014 0.018 c 0.20 C C 0.008 C C d 5.15 5.35 0.203 0.211 e 5.20 5.40 0.205 0.213 e 1.27 C C 0.050 C C h 7.70 8.10 0.303 0.319 l 0.50 0.80 0.020 0.031 a 0 10 0 10 n8 8 cp 0.10 0.004
17/20 m24256-a tssop14 - 14 lead thin shrink small outline note: 1. drawing is not to scale. tssop14-m 1 14 cp c l e e1 d a2 a a e b 7 8 a1 l1 tssop14 - 14 lead thin shrink small outline symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 5.000 4.900 5.100 0.1969 0.1929 0.2008 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.500 0.750 0.0236 0.0197 0.0295 l1 1.000 0.0394 a 0 8 0 8
m24256-a 18/20 sbga7 C 7 ball shell ball grid array C underside view (ball side) note: 1. drawing is not to scale. a sbga-01 a1 ball "1" b e2 e3 d1 d d3 d2 e e1 fe fd sbga7 C 7 ball shell ball grid array note: 1. no ball is closer than d2 to any other ball, thus giving an arrangement of equilateral triangles in which: e1 = d2/2 ; e2 = d2 ; e3 = 3xd2/2 d3 = ? 3xd2/2 ; d1 = d2 + ? 3xd2/2 symb. mm inches typ. min. max. typ. min. max. a 0.430 0.380 0.480 0.017 0.015 0.019 a1 0.180 0.150 0.210 0.007 0.006 0.008 b 0.350 0.320 0.380 0.014 0.013 0.015 d 3.555 3.525 3.585 0.140 0.138 0.142 d2 1 1.000 0.970 1.030 0.039 0.038 0.041 e 2.275 2.245 2.305 0.090 0.088 0.091 fd 1.278 0.050 fe 0.388 0.015 n7 7
19/20 m24256-a table 12. revision history date rev description of revision 17-apr-2000 1.2 sbga7(ea) package added on pp 1, 2, orderinfo, packagedata e1 and e0 are specified as having to be tied either to v cc or v ss 22-may-2001 1.3 -r voltage range removed lead soldering temperature in the absolute maximum ratings table amended depiction of start and stop condition on timing illustrations revised write mode sequences with wc =1 (data write inhibited) illustration updated write cycle polling flow chart using ack illustration updated references to psdip8 changed to pdip8, and package mechanical data updated document promoted from preliminary data to full data sheet 09-oct-2001 1.4 document moved from full data sheet to not for new design (please see the m24256-b data sheet for a suitable replacement device) 09-nov-2001 1.5 reference made to an1470, on replacing the m24256-a by the m24256-b specification of test condition for leakage currents in the dc characteristics table improved
m24256-a 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? november 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies austalia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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